The present invention is directed to non-volatile memory cell arrays and their methods of operation. More particularly, the invention provides a method for programming a memory cell in a non-volatile memory cell array that reduces punch through leakage in unselected memory cells. Merely by way of example, the invention has been applied to certain non-volatile memory arrays including floating gate and nitride charge storage materials. But it would be recognized that the invention has a much broader range of applicability.
Non-volatile memory (“NVM”) generally refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. Conventional NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed for long term storage of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
FIG. 1 is a cross-sectional view diagram of a conventional non-volatile memory cell structure. As shown, memory cell 100 has source 102 and drain 103 formed within substrate 101. Control gate 105 overlies a charge storage material 107. The charge storage material 107 is separated from the substrate by dielectric 108. The charge storage material 107 is separated from the control gate 105 by dielectric 106. Dielectric 108 is often a tunnel oxide, and dielectric 106 is often a composite oxide-nitride-oxide (ONO) layer.
The charge storage layer 107 can include different materials and compositions. In an example, the charge storage material 107 is a floating gate. In another example, a memory cell has a so-called SONOS (silicon-oxide-nitride-oxide-silicon) structure. The nitride layer serves as a charge storage layer 107.
Non-volatile memory cell 100 can be programmed using a channel hot electron programming method. In an example, the source 102 is grounded. The drain 103 is coupled to a 4-5V voltage. A gate voltage of 8-10V is applied to control gate 105. Hot electrons are generated in the channel region and injected into the charge storage material 107. These electrons cause memory cell 100 to be programmed to a high threshold voltage state.
As discussed above, certain high voltages are applied to a memory cell during cell programming. In a memory array that includes memory cells arrange in rows and columns, the drain terminals of multiple memory cells are usually connected to a bit line, and the control gates of multiple memory cells are often connected to a word line. During a programming operation, a high voltage intended for the selected cell is also applied to a number of unselected cells that are connected to the bit line. This high voltage appears on the drain terminals of unselected memory cells and can cause high electric fields and punch through leakage in the unselected memory cells. The leakage current can result in a high power consumption of the memory chip. The leakage current can also lead to long term reliability problems of the memory cells. With continued shrinkage of semiconductor devices, the problem of punch through leakage is becoming increasingly more serious.
Accordingly, there is a need for improved methods for operating non-volatile memory cells that can reduce punch through leakage current. There is also a need for improved non-volatile memory array structures that can utilize the improved operation methods.